An NMR system generally includes transceiver circuits for transmitting signals to a tested sample and receiving echo signals therefrom and a processor for analyzing the echo signals in order to obtain imaging and/or material information of the sample. Recently, significant efforts have been devoted to miniaturize traditional NMR systems, in particular NMR transceivers. The numerous advantages of miniaturization include low cost, portability, and the fact that a micro-coil tightly surrounding a small size sample increases the signal quality.
The practical design and construction of miniaturized NMR transceiver circuits, however, may present a number of difficulties. For example, it may be challenging to design an interface between multiple components in a radio-frequency (RF) receiver that provides the overall gain, bandwidth, noise figure and other parameters without degrading the performance when the components are connected. FIG. 1 illustrates an architecture of a conventional RF receiver 100 that includes several stages of amplification: a first stage 102 sets the overall noise performance of the receiver and a second stage 104 provides a certain amount of programmable gain to optimize the dynamic range of the analog-to-digital converter (ADC) used to digitize the output of the receiver. In addition, the RF receiver may incorporate a mixer 106 to down-convert the input signal to a lower frequency in order to relax the requirements on the ADC, and a combination of amplification, filtering, and buffering 108 may be employed following the mixer 106 to drive the ADC.
The receiver architecture described above can be implemented in either discrete or integrated form and is applicable to many other applications besides RF. In discrete implementations, the input and output impedance are typically matched to 50Ω to standardize the interface between different off-the-shelf components. This, however, is not practical for integrated solutions due to size and power constraints. Instead, most integrated solutions require the interface between the components to be custom designed for each chip. This leads to design burdens and increases in cost that can make it impractical to quickly reconfigure the receiver architecture to meet the needs of different applications.
Accordingly, there is a need for an approach that provides a standardized interface between individual components of an integrated receiver to allow different analog front-end configurations to be assembled quickly from a set of standard building blocks. Such an interface preferably does not degrade performance of the overall gain, bandwidth, noise figure and other parameters of each analog front-end configuration when connected.